The invention pertains to the field of cyclical redundancy codes calculation circuits for detecting errors in transmission of serial data over communication links. More particularly, the invention pertains to certain improvements in CRC calculation apparatus in integrated circuit form to conserve chip area.
Error detection and correction using codes and check bits has long been used to improve the reliability of data transfers between units on a network or units in a computer system such as disk or main memory and the central processing unit. The most common scheme is parity checking. In this scheme, parity check bits are added to the information bits to make the total number of bits which are logic 1's in a byte equal to a known number. However this scheme has the well known drawback that when the number of information bits becomes high, the level of redundancy in terms of check bits required becomes excessively high.
Another checking scheme exists called polynomial or cyclic coding. This scheme can be designed to perform with higher efficiencies, i.e., less redundancy, than the parity checking schemes. The high efficiency of these schemes is inducing designers to use them more and more frequently.
The general concepts of cyclic coding schemes are most easily understood through use of several mental aids. A convenient way of thinking of a bit stream of data in serial format consisting of K bits is to think of it as a polynomial in a dummy variable x with K terms. The bits of the message are the coefficients of the polynomial. Thus, if 100100011011 is the bit stream message, the polynomial may be written as: ##EQU1##
To compute the cyclic code check bits (hereafter CRC bits) on a message, another polynomial P(x) called a generating polynomial is chosen. The degree of this polynomial, i.e., its highest exponent value, is greater than zero but less than the degree of M(x). The generator polynomial has a non-zero coefficient in the x.sup.0 term. For a message of a given length, more than one generating polynomial can be specified. Several accepted standard generating polynomials exist. A standard 32 bit generating polynomial is defined for the Autodin II and Ethernet.TM. standard. This generating polynomial is found in the draft proposed American National Standard for FDDI Media Access Control X3T9.5/83-16 update of 6-01-84. This standard generator polynomial is: ##EQU2##
Cyclic check or CRC bit computation involves dividing the message polynomial by the generator polynomial to generate a quotient polynomial and a remainder polynomial. The quotient polynomial is discarded and the remainder polynomial coefficients are appended to the message polynomial as CRC check bits.
The combined message and check bits are then transmitted over the communication link and arrive at the receiver either modified or unmodified depending upon whether errors occurred during the transmission. Generally, the receiving apparatus divides the complete received message, including check bits, by the same generator polynomial which was used to generate the check bits at the transmitter end of the link. The result of this division is a zero remainder polynomial if no error occurred during the transmission. A non-zero remainder indicates the presence of an error.
The type of apparatus that is used to perform the above described calculation on serial format input data is shown in FIG. 1. FIG. 1 is a block diagram of a CRC checkbit calculation machine. The CRC checksum register 30 is comprised of a plurality of memory cells that store the CRC check bits. The outputs of these memory cells are coupled to the inputs of an array 32 of shifting links some of which are exclusive-OR gates as best seen in FIG. 2.
FIG. 2 is a detailed circuit diagram of the block diagram of FIG. 1. The most significant output bit from the checksum register 30 is exclusive-ORed by an input gate 34 with the incoming serial data stream of the message polynomial, and the output of the exclusive-OR gate 34 which performs this function is coupled to an input of all the other exclusive-OR gates in the array. The array shifting links which are not exclusive-OR gates are simple conductors which merely shift the incoming data one bit position left or toward the most significant bit position. The outputs of the shifting links of the array are coupled back to the data inputs of the checksum register 30 by a bus 36. The exclusive-OR gates in the array 32 as well as the straight through conductors have their outputs coupled to the input of the checksum register of the next most significant bit position relative to the bit position of the input bits positions for each shifting link from the checksum register. A bit clock signal on the line 38 clocks the raw serial format input data of the message polynomial into the input gate 34 and causes the checksum register to load the data from the bus 36 into its memory cells. After all the raw input data bits in the message have been clocked in, the checksum register 30 contents are the CRC check bits for the message bits so processed.
FIG. 3 illustrates the format of the composite data packet that is transmitted after calculation of the checkbits. The segment 40 is the message polynomial upon which the CRC bits were calculated. These message polynomial bits are transmitted simultaneously with the calculation of the CRC bits in that each time a bit is input to the gate 34, it is simultaneously transmitted. The segment 42 is the complement of the CRC bits stored in the checksum register 30 after all the bits in the segment 40 have been processed. The segment 42 is comprised of complement CRC bits so that when CRC bits are calculated on the receiving end on the combined segments 40 and 42, the remainder will come out zero. In some protocols, the checksum register is preset to all logic 1's before the CRC calculation starts. In such a case, when CRC checkbits are calculated on the combined packet consisting of segments 40 and 42, the remainder will not be all zeros but will represent a standard remainder polynomial. This remainder polynomial will result every time when CRC checkbits are calculated on the combined segments 40 and 42 regardless of the bit pattern in the message polynomial 40.
The CRC checkbits in the segment 42 are sent following the segment 40 by switching a multiplexer 44 with a select signal on the line 47 to deselect the serial data input line 46 and select the output line 48 of an inverter 50. The input of the inverter 50 is coupled to the output of the most significant bit position memory cell in the checksum register. The inverter 50 inverts the check bits as they are clocked out in serial fashion by the bit clock signal on the line 38. The composite packet comprised of segment 40 followed by the CRC checkbits 42 appears on the serial output line 52.
A problem arises with the architecture of FIG. 1 where no bit clock signal is available to clock in raw input data to the input gate 34. Some systems are byte oriented and only provide a byte clock signal for every eight bits. Such systems must be able to compute CRC bits by accepting one byte of raw input data at a time and simultaneously computing the CRC bits taking into account the effect of each bit in the raw input data byte. An architecture to accomplish this parallel CRC computation is shown in FIG. 4.
In FIG. 4, the array of shifting links is comprised of a plurality of rows of shifting links with each row assigned to process one of the bits of the raw input data byte. The raw input data byte is shown as the bits D7 through D0 coupled to the input gates on the left. Each of these input data bits is coupled to an input of one of the input exclusive-OR gates 66, 68, 70, 72, 74, 76, 78 and 80. Each of these input gates has its output coupled to an input of each exclusive-OR gate in its row and to the input of the least significant bit position shifting link in the next row. Thus each row in the array 56 acts like the shifting links row 32 in FIG. 1 except that its outputs are connected to the inputs of the next row. The first row has its inputs coupled to the outputs of the checksum register 30 and the last row has its outputs coupled to the inputs of the checksum register. Each row has one input of its input gate coupled to the output of one of the bits in the highest order byte in the checksum register, the first row being connected to the highest order bit and the second row being connected to the second most significant bit and so on for all the rows. Each shifting link in each row shifts its input bit one bit position toward the most significant bit position of the checksum register. The architecture of FIG. 4 therefore calculates CRC bits by processing 8 bits of raw input data at a time.
If the achitecture of FIG. 4 is to be integrated, several improvements can be made which save chip area and which enable the architecture to perform several functions which cannot be done with the architecture of FIG. 1. For example, to get the CRC bits out of the checksum register 30 in parallel format in the architecture of FIG. 1 or FIG. 4 requires that a conductor be connected to each output of the checksum register 30. For a 32 bit checksum register, this would require that a great deal of chip area be consumed by the output bus conductors. It would be useful if only the highest order byte of CRC outputs were connected to the output bus and the other bytes of CRC data were shifted into the highest order byte for output. This would cut down the number of conductors in the output bus from 32 to 8 thereby saving much chip area.
In some systems it is necessary to calculate a first set of CRC bits on a first data packet and a second set of CRC bits on a second data packet either immediatly following the first data packet or immediatly following transmission of the CRC checkbits calculated on the first data packet. It is customary in many CRC calculation machines to preset the contents of the checksum register to all logic 1's just before the start of the CRC calculation. This improves the performance of the CRC calculation machine in that input data strings having long strings of logic 0's will still affect the contents of the checksum register such that if there is a malfunction in the checksum register or the calculation array, the malfunction can be immediately detected. If the checksum register were not preset to all 1's, a defect in the checksum register or calculation array might not be detected in such a circumstance.
When separate CRC check bits are to be calculated on two back to back packets, there is no clock cycle between the first and second packets during which the checksum register can be preset by inputting all logic 1's into the memory cells. It would be useful to provide a way to preset the CRC calculation machine for the second data packet in such a situation where there is no spare clock cycle between the first packet and the second packet.
It is common in networks of computers to formulate data packets which have header bits which define the network and the particular node of that network to which is addressed a data message appended to the header bits. It is desirable in such situations to be able to calculate the CRC bits in either of two ways. The first way is to calculate a header CRC on the header bits, and then to calculate a data CRC on the data message. The second way is to calculate a header CRC on the header bits, and then to calculate a data CRC on the whole packet including the header bits, the header CRC check bits and the data message. It would be useful to provide a CRC calculation machine which could calculate CRC checkbits using either of these two methods.
In the token ring computer network environment where all nodes in the network are connected together in a ring by a single cable, it is common to have multibyte messages being sent along the network where the first byte has certain initial bits which can be changed on the fly by any node in the network. It is not desirable to include these initial bits which are subject to unpredictable changes which are not errors in the CRC calculation. Such changes would show up in the CRC check bits as errors if a change in one of these bits occurred while passing through a node between the transmitting and the receiving node. It would be useful to provide a CRC calculation machine which could calculate the CRC on a data packet using only a byte clock and still be able to exclude from the CRC calculation any number of initial bits in the first byte of a message.